Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis
Crossref DOI link: https://doi.org/10.1007/s10773-019-04271-9
Published Online: 2019-09-14
Published Print: 2019-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Bhat, Soha Maqbool
Ahmed, Suhaib http://orcid.org/0000-0003-3496-8856
Funding for this research was provided by:
TEQIP-III (1-5736612144)
Text and Data Mining valid from 2019-09-14
Version of Record valid from 2019-09-14
Article History
Received: 18 April 2019
Accepted: 30 August 2019
First Online: 14 September 2019