Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation
Crossref DOI link: https://doi.org/10.1007/s10825-016-0950-y
Published Online: 2017-01-30
Published Print: 2017-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Nilamani, S.
Ramakrishnan, V. N.
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