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Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs

Crossref DOI link: https://doi.org/10.1007/s10825-019-01353-z

Published Online: 2019-05-31

Published Print: 2019-09

Update policy: https://doi.org/10.1007/springer_crossmark_policy