Verilog-A modeling of a silicene-based p–n junction logic device: simulation and applications
Crossref DOI link: https://doi.org/10.1007/s10825-019-01410-7
Published Online: 2019-10-26
Published Print: 2020-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Bhatia, Inderdeep Singh https://orcid.org/0000-0001-6828-4829
Randhawa, Deep Kamal Kaur
Text and Data Mining valid from 2019-10-26
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Article History
First Online: 26 October 2019