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A single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET

Crossref DOI link: https://doi.org/10.1007/s10825-020-01475-9

Published Online: 2020-03-06

Published Print: 2020-06

Update policy: https://doi.org/10.1007/springer_crossmark_policy