A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis
Crossref DOI link: https://doi.org/10.1007/s10836-015-5515-7
Published Online: 2015-03-13
Published Print: 2015-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Pereira, Igor Gadelha
Dias, Leonardo Alves
de Souza, Cleonilson Protásio
Text and Data Mining valid from 2015-03-13