16- Layer PCB Channel Design with Minimum Crosstalk and Optimization of VIA and TDR Analysis
Crossref DOI link: https://doi.org/10.1007/s10836-019-05814-y
Published Online: 2019-07-04
Published Print: 2019-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kavitha, A. http://orcid.org/0000-0002-8921-4923
Kaitepalli, Ch. Sekhararao
Swaminathan, J. N. http://orcid.org/0000-0002-7520-4839
Ahemedali, Shaik
Text and Data Mining valid from 2019-07-04
Version of Record valid from 2019-07-04
Article History
Received: 2 January 2019
Accepted: 17 June 2019
First Online: 4 July 2019