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Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems: Analysis, Design, and Implementation

Crossref DOI link: https://doi.org/10.1007/s10836-024-06126-6

Published Online: 2024-07-05

Published Print: 2024-08

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Khairullah, Shawkat Sabah https://orcid.org/0000-0001-8142-8815
Funding

Funding for this research was provided by:

University of Mosul (University of Mosul)
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Text and Data Mining valid from 2024-07-05

Version of Record valid from 2024-07-05
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Article History

Received: 24 March 2024

Accepted: 25 June 2024

First Online: 5 July 2024

Declarations

:

: The author declares that he neither has competing interests nor relevant financial or non-financial conflict interests to disclose.

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