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Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction

Published Online: 2024-09-27

Published Print: 2024-08

Authors

A, Ahilan

Gorantla, Anusha

Kiruba, Gladys

Hamad, Asmaa A.

Hassan, Mohamed M.

N., Venkatram

T. V., Sindhu
License Information

Text and Data Mining valid from 2024-08-01

Version of Record valid from 2024-08-01
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Article History

Received: 22 January 2024

Accepted: 20 August 2024

First Online: 27 September 2024

Declarations

:

: The authors declare that they have no conflict of interest.

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