Patil, Akhilesh P.
Revadekar, Chetan C.
Kamble, Girish U.
Kundale, Somnath S.
Kadam, Sunil J.
Sutar, Santosh S.
Patil, Pramod J.
Dongale, Tukaram D. http://orcid.org/0000-0003-2536-6132
Funding for this research was provided by:
‘RUSA-Industry Sponsored Centre for VLSI System Design’, Maharashtra state
Article History
Received: 12 May 2022
Accepted: 7 September 2022
First Online: 20 September 2022
Declarations
:
: The authors declare that they have no conflict of interest.