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Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography

Crossref DOI link: https://doi.org/10.1007/s11042-019-7187-2

Published Online: 2019-01-24

Published Print: 2019-07

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Shet, K. Sathish http://orcid.org/0000-0001-9616-1439
Aswath, A. R.

Hanumantharaju, M. C.

Gao, Xiao-Zhi
License Information

Text and Data Mining valid from 2019-01-24
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Article History

Received: 10 July 2018

Revised: 18 December 2018

Accepted: 6 January 2019

First Online: 24 January 2019