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Design and analysis of carrier reservoir SOA based 2 × 1 MUX with enable input and implementing basic logic gates using MUX at 120 Gb/s

Published Online: 2024-09-05

Authors

Agarwal, Vipul

Pareek, Prakash

Gupta, Sumit

Singh, Lokendra

Balaji, Bukya

Dakua, Pratap Kumar
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Text and Data Mining valid from 2024-09-05

Version of Record valid from 2024-09-05
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Article History

Received: 15 April 2024

Accepted: 6 August 2024

First Online: 5 September 2024

Declarations

:

: The authors declare no competing interests.

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