Providing Reliability of Physical Systems: Fully Delay Testable Logical Circuit Design with Compact Representation of all PDF Test Pairs
Crossref DOI link: https://doi.org/10.1007/s11182-016-0650-x
Published Online: 2016-01-12
Published Print: 2016-01
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Matrosova, A. Yu.
Mitrofanov, E. V.
Akhynova, D. I.
Text and Data Mining valid from 2016-01-01
