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SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU–GPU heterogeneous architectures

Crossref DOI link: https://doi.org/10.1007/s11227-018-2389-3

Published Online: 2018-05-19

Published Print: 2018-07

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Gao, Lan https://orcid.org/0000-0001-5637-9417
Wang, Rui

Xu, Yunlong

Yang, Hailong

Luan, Zhongzhi

Qian, Depei

Zhang, Han

Cai, Jihong
Funding

Funding for this research was provided by:

National Key R&D Program of China (2017YFB0203201, 2017YFC0820100)

National Natural Science Foundation of China (61732002, 61202425)
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First Online: 19 May 2018