Design and analysis of SIC: a provably timing-predictable pipelined processor core
Crossref DOI link: https://doi.org/10.1007/s11241-019-09341-z
Published Online: 2019-11-15
Published Print: 2020-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Hahn, Sebastian http://orcid.org/0000-0002-8412-7716
Reineke, Jan http://orcid.org/0000-0002-3459-2214
Funding for this research was provided by:
Deutsche Forschungsgemeinschaft
Text and Data Mining valid from 2019-11-15
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Article History
First Online: 15 November 2019