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A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC

Crossref DOI link: https://doi.org/10.1007/s11265-015-0982-8

Published Online: 2015-03-04

Published Print: 2016-01

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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