Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction
Crossref DOI link: https://doi.org/10.1007/s11265-015-1000-x
Published Online: 2015-04-19
Published Print: 2016-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Ibrahim, Atef
Gebali, Fayez
Text and Data Mining valid from 2015-04-19
