Design and Analysis of Low Power Staircase Decoder Using Configurable Pipeline Stages and Asynchronous Control Mechanism
Crossref DOI link: https://doi.org/10.1007/s11265-026-01984-z
Published Online: 2026-01-31
Published Print: 2026-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Selvan, Selciya https://orcid.org/0009-0001-4927-8180
Bharathi, M.
Text and Data Mining valid from 2026-01-31
Version of Record valid from 2026-01-31
Article History
Received: 29 October 2024
Revised: 18 July 2025
Accepted: 18 January 2026
First Online: 31 January 2026