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Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture

Crossref DOI link: https://doi.org/10.1007/s11277-018-5385-2

Published Online: 2018-02-22

Published Print: 2018-10

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Udaiyakumar, R.

Joseph, Senoj

Sundararajan, T. V. P.

Vigneswaran, D.

Maheswar, R.

Amiri, Iraj S.
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First Online: 22 February 2018