Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology
Crossref DOI link: https://doi.org/10.1007/s11277-019-06978-8
Published Online: 2019-11-27
Published Print: 2020-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Tripathi, Suman Lata
Patel, Govind Singh
Text and Data Mining valid from 2019-11-27
Version of Record valid from 2019-11-27
Article History
First Online: 27 November 2019