High Reliability Soft Error Hardened Latch Design for Nanoscale CMOS Technology using PVT Variation
Crossref DOI link: https://doi.org/10.1007/s11277-022-10033-4
Published Online: 2022-10-31
Published Print: 2023-01
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Dhanushya, T.
Latha, T.
Text and Data Mining valid from 2022-10-31
Version of Record valid from 2022-10-31
Article History
Accepted: 30 August 2022
First Online: 31 October 2022
Declarations
:
: On behalf of all authors, the corresponding author states that there is no conflict of interest.