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Representation of an Improved Heterostructure Junctionless Tunneling FET Based on the Drain/Gate Oxide and Hetero-Dielectric Engineering

Crossref DOI link: https://doi.org/10.1007/s11664-019-07335-y

Published Online: 2019-06-20

Published Print: 2019-09

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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