Dual P+-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications
Crossref DOI link: https://doi.org/10.1007/s11664-022-09462-5
Published Online: 2022-02-12
Published Print: 2022-05
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Bavir, Mohammad
Abbasi, Abdollah http://orcid.org/0000-0001-6490-8745
Orouji, Ali Asghar
Text and Data Mining valid from 2022-02-12
Version of Record valid from 2022-02-12
Article History
Received: 1 July 2021
Accepted: 19 January 2022
First Online: 12 February 2022
Conflict of interest
: The authors declare that they have no conflict of interest.