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A Scalable Enhancement-Mode Junctionless SiC FET with Embedded P+ Pockets in the Oxide Layer for High-Temperature Applications

Published Online: 2022-12-12

Published Print: 2023-02

Authors

Baruah, Ratul Kumar https://orcid.org/0000-0002-7595-5421
Mahajan, Bikram Kishore

Routh, Sujay
Funding

Funding for this research was provided by:

Department of Biotechnology, INDIA (BT/20/NE/2011(01/08/2017))

DST (SR/FST/ET-II/2018/241)

AICTE (1-6382306131)
License Information

Text and Data Mining valid from 2022-12-12

Version of Record valid from 2022-12-12
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Article History

Received: 26 April 2022

Accepted: 26 October 2022

First Online: 12 December 2022

Conflict of interest

: The authors declare that they have no conflict of interest.

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