A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture
Crossref DOI link: https://doi.org/10.1007/s12046-019-1121-1
Published Online: 2019-05-07
Published Print: 2019-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Bhat, Kalpana G
Laxminidhi, T
Bhat, M S
Text and Data Mining valid from 2019-05-07
Article History
Received: 10 March 2018
Revised: 13 July 2018
Accepted: 7 March 2019
First Online: 7 May 2019