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Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

Crossref DOI link: https://doi.org/10.1007/s12046-023-02304-y

Published Online: 2023-11-04

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Jain, Manan

Kanzariya, Het

Joshi, Neel

Masharu, Yesha

Gajjar, Sachin

Shah, Dhaval https://orcid.org/0000-0002-2531-9590
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Text and Data Mining valid from 2023-11-04

Version of Record valid from 2023-11-04
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Article History

Received: 3 March 2022

Revised: 17 July 2023

Accepted: 27 July 2023

First Online: 4 November 2023