Statistical Modeling of Logic Gates and Flip-Flops for High Speed CMOS Circuits Applications
Crossref DOI link: https://doi.org/10.1007/s12633-016-9453-5
Published Online: 2016-10-27
Published Print: 2017-05
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Patil, Siddhasen R.
Gautam, D. K.
License valid from 2016-10-27
