Performance Investigation of Gate Engineered tri-Gate SOI TFETs with Different High-K Dielectric Materials for Low Power Applications
Crossref DOI link: https://doi.org/10.1007/s12633-019-00283-6
Published Online: 2019-11-04
Published Print: 2020-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Vimala, P. http://orcid.org/0000-0002-8247-6621
Samuel, T. S. Arun
Pandian, M. Karthigai
Funding for this research was provided by:
Defence Research and Development Organisation (ERIP/ER/1504753/M/01/1629)
Text and Data Mining valid from 2019-11-04
Version of Record valid from 2019-11-04
Article History
Received: 2 March 2019
Accepted: 24 September 2019
First Online: 4 November 2019