Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application
Crossref DOI link: https://doi.org/10.1007/s12633-020-00424-2
Published Online: 2020-03-13
Published Print: 2021-02
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Chattopadhyay, Ankush
Bose, Chayanika
Sarkar, Chandan K.
Text and Data Mining valid from 2020-03-13
Version of Record valid from 2020-03-13
Article History
Received: 9 December 2019
Accepted: 13 February 2020
First Online: 13 March 2020