Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for Low-Voltage Performance Optimization
Crossref DOI link: https://doi.org/10.1007/s12633-020-00659-z
Published Online: 2020-08-28
Published Print: 2021-09
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kumar, Naveen http://orcid.org/0000-0002-4765-1789
Raman, Ashish
Text and Data Mining valid from 2020-08-28
Version of Record valid from 2020-08-28
Article History
Received: 24 April 2020
Accepted: 18 August 2020
First Online: 28 August 2020