Article History
Received: 28 January 2021
Accepted: 16 December 2021
First Online: 14 January 2022
Declarations
:
: Not Applicable.
: The paper titled “Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current” is our original unpublished work and we are consent to participation and publication in the Silicon Journal.
: We the undersigned declare that the manuscript entitled “Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current” is original, has not been fully or partly published before and is not currently being considered for publication elsewhere.We confirm that the manuscript has been read and approved by all named authors and that there are no other persons who satisfied the criteria for authorship but are not listed. We further confirm that the order of authors listed in the manuscript has been approved by all of us.We understand that the Corresponding Author is the sole contact for the editorial process. The corresponding author "Vijay Kumar Magraiya" is responsible for communicating with the other authors about process, submissions of revisions and final approval of proofs.Corresponding Author:Vijay Kumar Magraiya.
: The major contributions of the paper are as follows:1. A comprehensive analysis on the state-of-the-art leakage reduction techniques.2. An analysis of the leakage reduction using CNTFET devices.3. An improved leakage reduction technique using dual chiral CNTFET in standard footerless and LECTOR based domino circuits.4. The simulation results show subthreshold leakage current reduction upto 97.3% at 25 °C and 99.76% at 110 °C.