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Performance Evaluation of Junctionless Double Surrounding Gate Si Nanotube MOSFET Using Triple and Quadruple Metal Gate Work Function Engineering for the Upcoming Sub 2 nm Technology Node

Crossref DOI link: https://doi.org/10.1007/s12633-025-03290-y

Published Online: 2025-04-04

Published Print: 2025-06

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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