Review of error correction for PUFs and evaluation on state-of-the-art FPGAs
Crossref DOI link: https://doi.org/10.1007/s13389-020-00223-w
Published Online: 2020-05-11
Published Print: 2020-09
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Hiller, Matthias
Kürzinger, Ludwig
Sigl, Georg
Funding for this research was provided by:
Fraunhofer Institute for Applied and Integrated Security (AISEC)
Text and Data Mining valid from 2020-05-11
Version of Record valid from 2020-05-11
Article History
Received: 30 April 2018
Accepted: 22 March 2020
First Online: 11 May 2020