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Development of chip shrink technology for lateral-type GaN based HFETs using SiO2/polyimide dual IMD layers

Crossref DOI link: https://doi.org/10.1007/s13391-014-4298-9

Published Online: 2015-03-10

Published Print: 2015-03

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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