Leakage Power Reduction in Deep Submicron VLSI Circuits Using Delay-Based Power Gating
Crossref DOI link: https://doi.org/10.1007/s40009-019-00848-4
Published Online: 2019-11-16
Published Print: 2020-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Thamaraimanalan, T.
Sampath, P.
Text and Data Mining valid from 2019-11-16
Version of Record valid from 2019-11-16
Article History
Received: 13 June 2018
Revised: 13 September 2019
Accepted: 5 November 2019
First Online: 16 November 2019