IP-Based Design and Analysis of Parallel Prefix Adder for FPGAs
Crossref DOI link: https://doi.org/10.1007/s40009-024-01536-8
Published Online: 2024-11-28
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Gupta, Tukur https://orcid.org/0000-0003-3853-7068
Verma, Gaurav
Akhter, Shamim
Text and Data Mining valid from 2024-11-28
Version of Record valid from 2024-11-28
Article History
Received: 20 March 2024
Revised: 27 September 2024
Accepted: 21 October 2024
First Online: 28 November 2024
Declarations
:
: The authors declare that no conflicts of interest exist with the publication of this manuscript.