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Circuit Level Realization of Low Latency Radix-4 Booth Scheme for Parallel Multipliers

Crossref DOI link: https://doi.org/10.1007/s40010-021-00745-w

Published Online: 2021-04-20

Published Print: 2022-06

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Rahnamaei, Ali https://orcid.org/0000-0002-8627-7259
Fatin, Gholamreza Zare
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Text and Data Mining valid from 2021-04-20

Version of Record valid from 2021-04-20
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Article History

Received: 9 August 2019

Revised: 23 March 2021

Accepted: 5 April 2021

First Online: 20 April 2021