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FPGA-Based High-Resolution DPWM Scheme Using Interleaving of Phase-Shifted Clock Pulses

Crossref DOI link: https://doi.org/10.1007/s40031-020-00438-9

Published Online: 2020-03-14

Published Print: 2020-04

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Bhardwaj, Kritika

Singh, Alok https://orcid.org/0000-0002-4655-6325
Borage, Mangesh

Ajnar, D. S.

Tiwari, Sunil
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Text and Data Mining valid from 2020-03-14

Version of Record valid from 2020-03-14
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Article History

Received: 8 June 2018

Accepted: 15 February 2020

First Online: 14 March 2020