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Displacement analysis in three configurations of Si0.5Ge0.5/Si junctionless gate-all-around FET: a study from device to binary and ternary circuit applications

Crossref DOI link: https://doi.org/10.1007/s40042-024-01159-8

Published Online: 2024-08-13

Published Print: 2024-10

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Ghoreishi, Neda

Navi, Keivan

Sabbaghi-Nadooshan, Reza

Esmaeldoust, Mohammad
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Text and Data Mining valid from 2024-08-13

Version of Record valid from 2024-08-13
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Article History

Received: 18 June 2024

Revised: 18 July 2024

Accepted: 29 July 2024

First Online: 13 August 2024

Declarations

:

: The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

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