Design an optimal digital phase lock loop with current-starved ring VCO using CMOS technology
Crossref DOI link: https://doi.org/10.1007/s41870-020-00587-6
Published Online: 2021-01-03
Published Print: 2021-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Yadav, Rekha https://orcid.org/0000-0001-9580-9766
Kumari, Usha
Text and Data Mining valid from 2021-01-03
Version of Record valid from 2021-01-03
Article History
Received: 16 July 2019
Accepted: 23 November 2020
First Online: 3 January 2021