Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes
Crossref DOI link: https://doi.org/10.1007/s42452-021-04539-y
Published Online: 2021-04-07
Published Print: 2021-05
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Mohapatra, E.
Dash, T. P. http://orcid.org/0000-0001-6370-8573
Jena, J.
Das, S.
Maiti, C. K.
Text and Data Mining valid from 2021-04-07
Version of Record valid from 2021-04-07
Article History
Received: 28 November 2020
Accepted: 26 March 2021
First Online: 7 April 2021
Declarations
:
: On behalf of all authors, the corresponding author states that there is no conflict of interest.