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Analysis Optimum Sizing of 12 T PCSA for High Speed Soft Error Tolerant Logic Circuits Design

Crossref DOI link: https://doi.org/10.1007/s42835-022-01096-1

Published Online: 2022-05-02

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Aruna, A. Ranjani https://orcid.org/0000-0002-0956-4668
Kamala, J.

Hanuman, C. R. S.

Vaithiyanathan, Dhandapani
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Text and Data Mining valid from 2022-05-02

Version of Record valid from 2022-05-02
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Article History

Received: 30 September 2021

Revised: 6 March 2022

Accepted: 10 April 2022

First Online: 2 May 2022