Document is current

Any future updates will be listed below

Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization

Crossref DOI link: https://doi.org/10.1007/s42979-025-04062-6

Published Online: 2025-07-14

Update policy: https://doi.org/10.1007/springer_crossmark_policy

About CrossMark