Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency
Crossref DOI link: https://doi.org/10.1007/978-3-319-73423-1_23
Published Online: 2017-12-24
Published Print: 2018
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Parmar, Harikrishna
Mehta, Usha
License valid from 2017-12-24