Design of Ultralow Voltage-Hybrid Full Adder Circuit Using GLBB Scheme for Energy-Efficient Arithmetic Applications
Crossref DOI link: https://doi.org/10.1007/978-981-10-7329-8_22
Published Online: 2018-01-26
Published Print: 2018
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Sanapala, Kishore
Shree, L. Rekha
Sakthivel, R.
License valid from 2018-01-01
Text and Data Mining valid from 2018-01-01
Chapter History
First Online: 26 January 2018