Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance
Crossref DOI link: https://doi.org/10.1007/978-981-10-7470-7_24
Published Online: 2017-12-21
Published Print: 2017
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Maheshwaram, Satish
Prakash, Om
Sharma, Mohit
Bulusu, Anand
Manhas, Sanjeev
License valid from 2017-01-01