Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL’s 0.18 µm CMOS Process
Crossref DOI link: https://doi.org/10.1007/978-981-10-7470-7_63
Published Online: 2017-12-21
Published Print: 2017
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Malik, Munish
Kumar, Ajay
Jatana, H. S.
License valid from 2017-01-01