Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA
Crossref DOI link: https://doi.org/10.1007/978-981-10-8533-8_13
Published Online: 2018-05-16
Published Print: 2018
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Thind, Vandana
Pandey, Sujeet
Akbar Hussain, D. M.
Das, Bhagwan
Abdullah, M. F. L.
Pandey, Bishwajeet
License valid from 2018-01-01