Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire)
Crossref DOI link: https://doi.org/10.1007/978-981-13-1513-8_62
Published Online: 2018-09-13
Published Print: 2019
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kulkarni, Shreyas
Joshi, Sangeeta
Bade, Dattatray
Subramaniam, Subha
Text and Data Mining valid from 2018-09-13