Leakage Reduction in Full Adder Circuit Using Source Biasing at 45 nm Technology
Crossref DOI link: https://doi.org/10.1007/978-981-13-2553-3_29
Published Online: 2018-11-20
Published Print: 2019
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Goyal, Candy
Singh Ubhi, Jagpal
Raj, Balwinder
Text and Data Mining valid from 2018-11-20